`include "../include/cpu_defines.sv"

module IDRAT_reg(
	input logic cpu_clk,
	input logic stall,
	input logic clear,
	input logic [5: 0] id_inst_rs,
	input logic [5: 0] id_inst_rt,
	input logic [5: 0] id_inst_rd,
	input logic [31: 0] id_inst_src1,
	input logic [31: 0] id_inst_src2,
	input logic [`INST_TYPE_BUS] id_inst_type,
	input logic [`ALUOP_BUS] id_inst_aluop,
	input logic id_inst_en,
	input logic [`MEMOP_BUS] id_inst_memop,
	input logic [`EXC_CODE_BUS] id_inst_exccode,
	input logic [`CP0OP_BUS] id_inst_cp0op,
	input logic [`MULTOP_BUS] id_inst_multop,
	input logic id_inst_place2,
	input logic id_inst_branch,
	input logic id_inst_rasup,
	input logic id_inst_rasdown,
	`ifdef CPU_DEBUG
		input logic [31:0] debug_idrat_inst_in,
		input logic [31:0] debug_idrat_addr_in,
		output logic [31:0] debug_idrat_inst_out,
		output logic [31:0] debug_idrat_addr_out,
	`endif
	output logic [5: 0] rat_inst_rs,
	output logic [5: 0] rat_inst_rt,
	output logic [5: 0] rat_inst_rd,
	output logic [31: 0] rat_inst_src1,
	output logic [31: 0] rat_inst_src2,
	output logic [`INST_TYPE_BUS] rat_inst_type,
	output logic [`ALUOP_BUS] rat_inst_aluop,
	output logic rat_inst_en,
	output logic [`MEMOP_BUS] rat_inst_memop,
	output logic [`EXC_CODE_BUS] rat_inst_exccode,
	output logic [`CP0OP_BUS] rat_inst_cp0op,
	output logic [`MULTOP_BUS] rat_inst_multop,
	output logic rat_inst_place2,
	output logic rat_inst_branch,
	output logic rat_inst_rasup,
	output logic rat_inst_rasdown
);

	always_ff @(posedge cpu_clk)begin
		if(clear || !id_inst_en && !stall)begin
			rat_inst_rs <= 0;
			rat_inst_rt <= 0;
			rat_inst_rd <= 0;
			rat_inst_src1 <= 0;
			rat_inst_src2 <= 0;
			rat_inst_type <= 0;
			rat_inst_aluop <= 0;
			rat_inst_en <= 0;
			rat_inst_memop <= 0;
			rat_inst_exccode <= `EXC_NONE;
			rat_inst_cp0op <= 0;
			rat_inst_multop <= 0;
			rat_inst_place2 <= 0;
			rat_inst_branch <= 0;
			rat_inst_rasup <= 0;
			rat_inst_rasdown <= 0;
			`ifdef CPU_DEBUG
				debug_idrat_inst_out <= 0;
				debug_idrat_addr_out <= 0;
			`endif
		end
		else if(~stall)begin
			rat_inst_rs <= id_inst_rs;
			rat_inst_rt <= id_inst_rt;
			rat_inst_rd <= id_inst_rd;
			rat_inst_src1 <= id_inst_src1;
			rat_inst_src2 <= id_inst_src2;
			rat_inst_type <= id_inst_type;
			rat_inst_aluop <= id_inst_aluop;
			rat_inst_en <= id_inst_en;
			rat_inst_memop <= id_inst_memop;
			rat_inst_exccode <= id_inst_exccode;
			rat_inst_cp0op <= id_inst_cp0op;
			rat_inst_multop <= id_inst_multop;
			rat_inst_place2 <= id_inst_place2;
			rat_inst_rasup <= id_inst_rasup;
			rat_inst_rasdown <= id_inst_rasdown;
			`ifdef CPU_DEBUG
				debug_idrat_inst_out <= debug_idrat_inst_in;
				debug_idrat_addr_out <= debug_idrat_addr_in;
			`endif
			rat_inst_branch <= id_inst_branch;
		end
	end


endmodule